Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!
E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.
We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.
We are seeking an experienced Senior Digital Backend Layout Engineer specializing in Place and Route (P&R) to join our semiconductor engineering team. In this role, you will lead and execute the backend flow of digital ASIC designs from synthesis through to GDSII. Your primary focus will be on optimizing layout for area, power, and performance while ensuring DRC/LVS compliance. You’ll work closely with design and verification engineers to integrate frontend logic with backend physical design, meeting strict deadlines and quality standards for advanced semiconductor technologies.
What you will be doing:
Physical Implementation: Manage end-to-end backend physical design flow, including floor planning, placement, routing, and timing optimizationPower and Performance Optimization: Optimize layout for power efficiency, timing closure, and area, ensuring alignment with project specifications and industry standardsTiming Analysis and Closure: Perform Static Timing Analysis (STA) and drive timing closure, working collaboratively with frontend and verification teamsDRC/LVS Compliance: Ensure designs are DRC (Design Rule Check) and LVS (Layout Versus Schematic) compliant using industry-standard toolsTool Utilization and Scripting: Proficiency with industry-standard EDA tools for P&R, STA, and verification (e.g., Cadence Innovus, Synopsys ICC2, Mentor Calibre) and scripting languages (e.g., TCL, Python, Perl) for flow customization and automationCross-functional Collaboration: Work closely with digital design, verification, and RF/analog layout teams to ensure successful integration of all componentsDocumentation and Reporting: Maintain accurate and up-to-date documentation of design methodologies, processes, and results, reporting to project leads and management
What you bring to this role:
5+ years in digital backend design, with a strong track record of successful P&R and tape-out in advanced process nodes (e.g., 7nm, 5nm)Proficiency with physical design tools such as Cadence Innovus, Synopsys ICC2, Mentor Calibre, etc.Strong knowledge of timing analysis, clock tree synthesis, IR drop analysis, and EM checksFamiliarity with physical verification techniques, including DRC, LVS, and PEXScripting experience with TCL, Python, or Perl for tool automationStrong verbal and written communication skills to collaborate across teams and present complex technical concepts effectively
Bonus Points:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
